The present invention relates generally to semiconductor device processing techniques and, more particularly, to a test structure and method for detecting via contact shorting above shallow trench isolation (STI) regions of a semiconductor device.
As the size of integrated circuit devices continues to shrink, the level of integration increases while the structures for electrically isolating devices also reduces correspondingly. For example, the conventional field oxide layer formed by the local oxidation of silicon (LOCOS) method is no longer suitable as an isolation structure when the device is increasingly miniaturized, due in part to the so-called bird's beak encroachment that often leads to the production of leakage current.
Because of the difficulties in fabricating miniaturized isolating devices, other methods of isolating devices have been developed. One of the most widely adopted isolation methods for sub micron devices is to form a shallow trench isolation (STI) structure, wherein trenches are defined within a substrate surface and then prepared for filling with dielectric materials. The resulting trenches typically display a steep sidewall profile as compared to LOCOS oxidation. The trenches are subsequently refilled with a dielectric such as chemical vapor deposited (CVD) silicon dioxide (SiO2). In contrast, “active” regions are regions in which active devices (e.g., source/drain diffusions) are fabricated, and which lie between the trenches.
Before formation of metal via contacts, it is usually required to deposit a protection layer (most commonly using nitride) to protect devices from mobile ions and moisture, as well as to provide a etch stopper for etching contact holes. One problem, however, associated with decreasing device size and pitch (spacing) between structures such as transistor gate electrodes is that of voiding when protection layers are conformally deposited over the gate and spacer structures. The voids are easily formed when an aspect ratio between gate height and pitch is high. Due to multiple steps of etching, cleaning, and photoresist stripping before depositing the protection layer, the surface level of STI regions is much lower than active area (i.e., the Si surfaces). Therefore, the aspect ratio between gate height and pitch in STI regions usually is larger than that in active areas. Thus, the voids are more easily formed above STI areas than active areas. In some cases, the voids are formed only above STI regions and not at all formed in active areas.
Consequently, when an insulative material (e.g., oxide) is then blanket deposited over the protection layer, the pinching of protection layer prevents the oxide from filling the voids. Then, during subsequent via formation, the metal fill material (e.g., tungsten or TiN) can also end up filling the void if the via contact holes connect to the void, thereby creating undesirable “stringers” that can short adjacent vias to one another. Accordingly, it is desirable to be able to efficiently detect a potential stringer problem in the formation of such semiconductor devices.